1. Field of the Invention
The present invention relates in general to a semiconductor memory device, and more particularly, to a volatile memory structure with an improved buried strap and method for forming the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) device is a typical volatile memory device for integrated circuit devices. A DRAM cell includes an access transistor and a storage capacitor. In the fabrication of the integrated circuit devices, a buried strap has been employed in fabricating deep trench-based DRAM devices. The buried strap is a critical in connecting the storage capacitor to the access transistor. Accordingly, the resistivity of the buried strap and the buried strap width are important factors in providing excellent interconnect properties between transistors and capacitors. The buried strap width is subject to the active area of the deep trench overlay.
FIG. 1 is a cross-section showing a conventional deep trench-based DRAM structure. The DRAM structure includes a substrate 100 having a plurality of pairs of neighboring trenches formed therein. A pair of neighboring trenches 101 is shown for simplicity. Two buried trench capacitors 105 are respectively disposed in a lower portion of each trench 101. The capacitor 105 includes a buried bottom plate 102 formed in the substrate 100 around the lower portion of the trench 101, a top plate 104 disposed in the lower portion of the trench 101, and a capacitor dielectric layer 103 disposed between the buried bottom plate 102 and the top plate 104. Two collar oxide layers 106 are respectively disposed over an upper portion of the sidewall of each trench 101, and two first conductive layers 108 are respectively disposed in the upper portion of each trench 101 and surrounded by the collar oxide layers 106. Two second conductive layers 110 are respectively disposed overlying the collar oxide layer 106 and the first conductive layer 108 in each trench 101. A shallow trench isolation (STI) structure 112 is disposed between the neighboring trenches 101 to serve as an isolation region between the buried trench capacitors 105. Access transistors 114 are disposed overlying the substrate 100 outside of the pair of the neighboring trench 101, which includes a gate 114, a gate dielectric layer 113, and a source/drain region 115. Two gates 117 are respectively disposed on the STI structure 112 over each trench 101.
However, according to the conventional DRAM structure, the width of the first conductive layer 108 and the second conductive layer 110 are narrowed due to formation of the STI structure 112. Therefore, the contact resistance is increased, reducing the saturation drain current and resulting in signal margin failure.
FIG. 2 is a plane view of the pair of the neighboring trenches before forming the STI structure in FIG. 1. Conventionally, in order to leave a space for forming the STI structure, an island photoresist pattern is used for defining the active area AA. However, the precise alignment between the active area AA and the trench 101 is difficult, especially as the size memory devices are continuously reduced. Therefore, the process window of the active area to the trench overlay decreases due to misalignment during lithography.